Humour me with letting me describe what I'm seeing in the simulations about how a LTP PI clips. They match things I've seen on the CRO from a real circuit, but haven't captured yet. A couple of years ago when I said grid clipping current was drawn through the 3rd stage to PI coupling cap, I assumed it occurred when the input got above the cathode voltage. It actually happens later than that.
Within linear operation you all know what happens. The pin 7 grid goes up, a small amount of signal gets fed to pin 2 grid via the presence pot in the tail, more signal gets fed to pin 2 grid via the feedback, and the cathodes sit in the middle of these two. Pin 6 plate drops and pin 1 plate rises. Everything looks nice and fairly linear. With a negative swing on the input same but in reverse direction.
When the first stage of clipping happens depends on the bias. In an Express we've got a shared 470R cathode bias resistor. This biases the grids at around -1V compared to the cathodes. Put in a bit over 2V positive signal swing and the pin 7 grid and cathode voltage are equal. Over that and the grid signal pulls up the cathodes so that they stay pretty close to the grid. This results in the pin 6 plate rounded bottom to it's signal. Pin1 plate in the mean time has gone up as far as it will because this side is cut-off. At this point the pin 7 input grid isn't conducting any real current. With the cathodes able or free to come up, this side isn't really going into grid clipping but just holding on the edge of it to pull up the cathodes.
Go the other way with a higher negative signal and the pin 2 grid clamps the cathodes and holds them just under the grid voltage. Pin 7 grid input can continue as low as it likes but now has no effect. The pin 6 plate is as high as it will go as that side is cut-off. The pin 1 plate negative side is flat clipped because of the fixed difference between the pin 2 grid and the cathodes because of this clamping or holding.
Increase the signal and things stay like this for a while, until you hit the point where the pin 6 plate reduces enough compared to the rising cathodes that you hit valve saturation (something you don't see very often). From my posted waveforms, at Volume 6.5 (with biggest duty cycle shift) the PI power node is about 240V, pin 6 plate is roughly 120V, and the cathodes peak is about 28V. We can't trust the grid DC values because of CRO loading. But that equates to an available 240-28 = 212V supply to cathode, with 120-28 = 92V actually across plate to cathode. Draw that as a load line on the 12AX7 characteristics with an 82K load and the intersection with the Vg=0V line is about 75V at 1.65mA. With 240-120 = 120V across the 82K plate resistor we're actually drawing 1.46mA at that point in the signal, at the measured 92V plate to cathode. OK, it doesn't quite line up, but within the tolerance of the installed valve I'd say that's enough to indicate we're at saturation or bloody close to it. At saturation the simulation shows that the rising cathode lifts up into the plate signal and creates an inverted peak (same as what happens on a saturated BJT transistor stage). It's at this point where grid current is drawn from the previous stage through the coupling cap. The cap charges up to drop the PI input grid waveform until it stops peaking enough to drive this side of the PI into saturation. This shift has a clamping effect, and the bigger the drive into the PI the more the signal moves down until the positive peak is clamped around the same position.
This finally explains to me why this shifting and clamping doesn't result in blocking distortion. It's ingenious! In a normal gain stage the clipping and clamping happen at the same point. In a LTP PI the plates reach cut-off on respective sides, but clamping of the input only happens at a larger input swing. There's always a bit of headroom between the two so when the signal backs off it's not sitting below cut-off.
Aiken touches on this: "An interesting thing can happen, though, when the phase inverter hits clipping. This very high input impedance suddenly drops, and can severely clip the input waveform (by "clamping" the top to the cathode voltage level) and raise the lower -3dB point."
http://www.aikenamps.com/index.php/the-long-tail-pair
He doesn't explain how it works, but with the above now we know.
I also found a couple of other vague references to the loss of bass response with LTP PI clipping as well.
In the simulation it's when the inverting side reaches saturation and the input grid signal starts shifting down that we get the introduction of asymmetry. The input grid signal shift down meaning relative to the other grid and cathodes it's working with only the top section of the sine wave. The new 'zero crossing' reference being elevated relative to the true sine wave centre point means that the positive peak is narrow and the negative the wider side. That translates through the PI, power stage and OT into the top of the speaker output also being narrow and the bottom wider - our shift in duty cycle.
The beauty of simulation that I'm not getting with the CRO shots is at time 0 sec the circuit is at no signal steady state. On the CRO everything has moved already. You can see the clipping and movement downwards of the PI input grid signal clear as day at the start of the simulation. I'll get together some simulation shots that show what I'm talking about. After that I've got to play around with my CRO and see if I can get it to one-shot capture to replicate testing the same thing on the real circuit. I've had the CRO for years but only ever used it in the conventional mode.
